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DATA SHEET
PD442000A-X
2M-BIT CMOS STATIC RAM 256K-WORD BY 8-BIT EXTENDED TEMPERATURE OPERATION
MOS INTEGRATED CIRCUIT
Description
The PD442000A-X is a high speed, low power, 2,097,152 bits (262,144 words by 8 bits) CMOS static RAM. The PD442000A-X has two chip enable pins (/CE1, CE2) to extend the capacity. And battery backup is available. The PD442000A-X is packed in 32-pin PLASTIC TSOP (I) (Normal bent) and 32-pin PLASTIC TSOP (I) (Reverse bent).
Features
* 262,144 words by 8 bits organization * Fast access time : 55, 70, 85, 100, 120 ns (MAX.) * Low voltage operation : VCC = 2.7 to 3.6 V (-BB55X, -BB70X, -BB85X) VCC = 2.2 to 3.6 V (-BC70X, -BC85X, -BC10X) VCC = 1.8 to 2.2 V (-DD85X, -DD10X, -DD12X) * Low VCC data retention : 1.0 V (MIN.) * Operating ambient temperature : TA = -25 to +85 C * Output Enable input for easy application * Two Chip Enable inputs : /CE1, CE2
PD442000A
Access time ns (MAX.) Operating supply Operating ambient voltage V -BB55X, -BB70X, -BB85X -BC70X, -BC85X, -BC10X -DD85X, -DD10X, -DD12X 55, 70, 85 70, 85, 100 85, 100, 120 2.7 to 3.6 2.2 to 3.6 1.8 to 2.2 temperature C -25 to +85 At operating mA (MAX.) 30
Note
Supply current At standby At data retention
A (MAX.)
2
A (MAX.)
1
30 15 1.5
Note Cycle time 70 ns, -BB55X : 35 mA
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. M14669EJ7V0DS00 (7th edition) Date Published October 2002 NS CP (K) Printed in Japan
The mark 5 shows major revised points.
(c)
2000
PD442000A-X
Ordering Information
Part number Package Access time ns (MAX.) Operating supply voltage V Operating temperature C -25 to +85
PD442000AGU-BB55X-9JH PD442000AGU-BB70X-9JH PD442000AGU-BB85X-9JH PD442000AGU-BC70X-9JH PD442000AGU-BC85X-9JH PD442000AGU-BC10X-9JH PD442000AGU-DD85X-9JH PD442000AGU-DD10X-9JH PD442000AGU-DD12X-9JH PD442000AGU-BB55X-9KH PD442000AGU-BB70X-9KH PD442000AGU-BB85X-9KH PD442000AGU-BC70X-9KH PD442000AGU-BC85X-9KH PD442000AGU-BC10X-9KH PD442000AGU-DD85X-9KH PD442000AGU-DD10X-9KH PD442000AGU-DD12X-9KH
32-pin PLASTIC TSOP (I) (8x13.4) (Normal bent)
55 70 85 70 85 100 85 100 120
2.7 to 3.6
2.2 to 3.6
1.8 to 2.2
32-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent)
55 70 85 70 85 100 85 100 120
2.7 to 3.6
2.2 to 3.6
1.8 to 2.2
2
Data Sheet M14669EJ7V0DS
PD442000A-X
Pin Configurations
/xxx indicates active low signal. 32-pin PLASTIC TSOP (I) (8x13.4) (Normal bent) x [ PD442000AGU-9JH ]
Marking Side
A11 A9 A8 A13 /WE CE2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
/OE A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3
A0 to A17
: Address inputs
I/O1 to I/O8 : Data inputs / outputs /CE1, CE2 /WE /OE VCC GND : Chip Enable 1, 2 : Write Enable : Output Enable : Power supply : Ground
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M14669EJ7V0DS
3
PD442000A-X
32-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent) x [ PD442000AGU-9KH ]
Marking Side
/OE A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A11 A9 A8 A13 /WE CE2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4
A0 to A17
: Address inputs
I/O1 to I/O8 : Data inputs / outputs /CE1, CE2 /WE /OE VCC GND : Chip Enable 1, 2 : Write Enable : Output Enable : Power supply : Ground
Remark Refer to Package Drawings for the 1-pin index mark.
4
Data Sheet M14669EJ7V0DS
PD442000A-X
Block Diagram
VCC GND A0 A17
Address buffer
Row decoder
Memory cell array 2,097,152 bits
I/O1 I/O8
Input data controller
Sense amplifier / Switching circuit Column decoder
Output data controller
Address buffer
/CE1 CE2
/OE
/WE
Truth Table
/CE1 H x L L L CE2 x L H H H /OE x x H L x /WE x x H H L Mode Not selected Not selected Output disable Read Write I/O High-Z High-Z High-Z DOUT DIN ICCA Supply current ISB
Remark x : VIH or VIL
Data Sheet M14669EJ7V0DS
5
PD442000A-X
Electrical Specifications
Absolute Maximum Ratings
Parameter Symbol Condition -BB55X, -BB70X, -BB85X -BC70X, -BC85X, -BC10X Supply voltage Input / Output voltage Operating ambient temperature Storage temperature VCC VT TA Tstg -0.5
Note
Rating -DD85X, -DD10X, -DD12X
Unit
-0.5 Note to +4.0 to VCC+0.4 (4.0 V MAX.) -0.5 -25 to +85 -55 to +125
Note
-0.5 Note to +2.7 to VCC+0.4 (2.7 V MAX.) -25 to +85 -55 to +125
V V C C
Note -3.0 V (MIN.) (Pulse width : 30 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Symbol Condition
-BB55X,-BB70X,-BB85X -BC70X,-BC85X,-BC10X -DD85X,-DD10X,-DD12X Unit
MIN. Supply voltage High level input voltage VCC VIH 2.7 V VCC 3.6 V 2.2 V VCC < 2.7 V 1.8 V VCC < 2.2 V Low level input voltage Operating ambient temperature VIL TA 2.7 2.4 - - -0.3
Note
MAX. 3.6 VCC+0.4 - - +0.5 +85
MIN. 2.2 2.4 2.0 - -0.3
Note
MAX. 3.6 VCC+0.4 VCC+0.3 - +0.4 +85
MIN. 1.8 - - 1.6 -0.2
Note
MAX. 2.2 - - VCC+0.2 +0.2 +85 V C V V
-25
-25
-25
Note -1.0 V (MIN.) (Pulse width : 20 ns) Capacitance (TA = 25 C, f = 1 MHz)
Parameter Input capacitance Input / Output capacitance Symbol CIN CI/O VIN = 0 V VI/O = 0 V Test condition MIN. TYP. MAX. 8 10 Unit pF pF
Remarks
1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are not 100% tested.
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Data Sheet M14669EJ7V0DS
PD442000A-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2)
Parameter Symbol Test condition -BB55X, -BB70X, -BB85X MIN. Input leakage current I/O leakage current ILI ILO VIN = 0 V to VCC VI/O = 0 V to VCC, /CE1 = VIH or CE2 = VIL or /WE = VIL or /OE = VIH Operating supply current ICCA1 /CE1 = VIL, CE2 = VIH, Minimum cycle time, II/O = 0 mA ICCA2 /CE1 = VIL, CE2 = VIH, Cycle time = , II/O = 0 mA ICCA3 /CE1 0.2 V, CE2 VCC - 0.2 V, Cycle time = 1 s, II/O = 0 mA, VIL 0.2 V, VIH VCC - 0.2 V Standby supply current ISB ISB1 ISB2 High level output voltage Low level output voltage VOH VOL /CE1 = VIH or CE2 = VIL /CE1 VCC - 0.2 V, CE2 VCC - 0.2 V CE2 0.2 V IOH = -0.5 mA IOL = 1.0 mA 2.4 0.4 - 0.1 0.1 0.35 2 2 V V mA - 4 - 4 Cycle time = 55 ns Cycle time 70 ns - - 35 30 mA -1.0 -1.0 TYP. MAX. +1.0 +1.0 Unit
A A
A
Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of product classification.
Data Sheet M14669EJ7V0DS
7
PD442000A-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2)
Parameter Symbol Test condition
-BC70X, -BC85X, -BC10X -DD85X, -DD10X, -DD12X
Unit
MIN. Input leakage current I/O leakage current ILI ILO VIN = 0 V to VCC VI/O = 0 V to VCC, /CE1 = VIH or CE2 = VIL or /WE = VIL or /OE = VIH Operating supply current ICCA1 /CE1 = VIL, CE2 = VIH, Minimum cycle time, II/O = 0 mA ICCA2 /CE1 = VIL, CE2 = VIH, Cycle time = , II/O = 0 mA ICCA3 VCC 2.7 V VCC 2.2 V VCC 2.7 V VCC 2.2 V -1.0 -1.0
TYP.
MAX. +1.0 +1.0
MIN. -1.0 -1.0
TYP.
MAX. +1.0 +1.0
A A
- - - - - - -
30 25 - 4 2 - 4
- - - - - - -
- - 15 - - 1 -
mA
/CE1 0.2 V, CE2 VCC - 0.2 V, Cycle time = 1 s, II/O = 0 mA, VIL 0.2 V, VIH VCC - 0.2 V VCC 2.7 V VCC 2.2 V
- - -
3 - 0.35 0.35 - 2 2 - 2 2 - - - 1.5 0.4
- - - - - - - 0.05 - - 0.05
- 3 - - 0.35 - - 1.5 - - 1.5 V mA
Standby supply current
ISB
/CE1 = VIH or CE2 = VIL VCC 2.7 V VCC 2.2 V
- - 0.1
ISB1
/CE1 VCC - 0.2 V, CE2 VCC - 0.2 V VCC 2.7 V VCC 2.2 V
A
0.08 - 0.1
ISB2
CE2 0.2 V VCC 2.7 V VCC 2.2 V
0.08 - 2.4
High level output voltage
VOH
IOH = -0.5 mA VCC 2.7 V VCC 2.2 V
1.8 -
Low level output voltage
VOL
IOL = 1.0 mA VCC 2.7 V VCC 2.2 V
- - 0.4
V
0.4 -
Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of product classification.
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Data Sheet M14669EJ7V0DS
PD442000A-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions Input Waveform (Rise and Fall Time 5 ns)
0.9 VCC VCC/2 0.1 VCC Test points VCC/2
Output Waveform
VCC/2
Test points
VCC/2
Output Load [ -BB55X, -BB70X, -BB85X ] 1TTL + 50 pF [ -BC70X, -BC85X, -BC10X, -DD85X, -DD10X, -DD12X ] 1TTL + 30 pF
Data Sheet M14669EJ7V0DS
9
PD442000A-X
Read Cycle (1/3)
Parameter Symbol -BB55X MIN. Read cycle time Address access time /CE1 access time CE2 access time /OE to output valid Output hold from address change /CE1 to output in Low-Z CE2 to output in Low-Z /OE to output in Low-Z /CE1 to output in High-Z CE2 to output in High-Z /OE to output in High-Z tRC tAA tCO1 tCO2 tOE tOH tLZ1 tLZ2 tOLZ tHZ1 tHZ2 tOHZ 10 10 10 5 20 20 20 55 55 55 55 30 10 10 10 5 25 25 25 MAX. VCC 2.7 V -BB70X MIN. 70 70 70 70 35 10 10 10 5 30 30 30 MAX. -BB85X MIN. 85 85 85 85 40 MAX. ns ns ns ns ns ns ns ns ns ns ns ns Note 2 Note 1 Unit Condition
Notes 1. The output load is 1TTL + 50 pF. 2. The output load is 1TTL + 5 pF.
Read Cycle (2/3)
Parameter Symbol -BC70X MIN. Read cycle time Address access time /CE1 access time CE2 access time /OE to output valid Output hold from address change /CE1 to output in Low-Z CE2 to output in Low-Z /OE to output in Low-Z /CE1 to output in High-Z CE2 to output in High-Z /OE to output in High-Z tRC tAA tCO1 tCO2 tOE tOH tLZ1 tLZ2 tOLZ tHZ1 tHZ2 tOHZ 10 10 10 5 25 25 25 70 70 70 70 35 10 10 10 5 30 30 30 MAX. VCC 2.2 V -BC85X MIN. 85 85 85 85 40 10 10 10 5 35 35 35 MAX. -BC10X MIN. 100 100 100 100 50 MAX. ns ns ns ns ns ns ns ns ns ns ns ns Note 2 Note 1 Unit Condition
Notes 1. The output load is 1TTL + 30 pF. 2. The output load is 1TTL + 5 pF.
10
Data Sheet M14669EJ7V0DS
PD442000A-X
Read Cycle (3/3)
Parameter Symbol -DD85X MIN. Read cycle time Address access time /CE1 access time CE2 access time /OE to output valid Output hold from address change /CE1 to output in Low-Z CE2 to output in Low-Z /OE to output in Low-Z /CE1 to output in High-Z CE2 to output in High-Z /OE to output in High-Z tRC tAA tCO1 tCO2 tOE tOH tLZ1 tLZ2 tOLZ tHZ1 tHZ2 tOHZ 10 10 10 5 30 30 30 85 85 85 85 40 10 10 10 5 35 35 35 MAX. VCC 1.8 V -DD10X MIN. 100 100 100 100 50 10 10 10 5 40 40 40 MAX. -DD12X MIN. 120 120 120 120 60 MAX. ns ns ns ns ns ns ns ns ns ns ns ns Note 2 Note 1 Unit Condition
Notes 1. The output load is 1TTL + 30 pF. 2. The output load is 1TTL + 5 pF.
Data Sheet M14669EJ7V0DS
11
PD442000A-X
Read Cycle Timing Chart
tRC
Address (Input) tAA /CE1 (Input) tCO1 tLZ1 tHZ1 tOH
CE2 (Input)
tCO2 tLZ2 tHZ2
/OE (Input) tOE tOLZ I/O (Output) High-Z Data out tOHZ
Remark In read cycle, /WE should be fixed to high level.
12
Data Sheet M14669EJ7V0DS
PD442000A-X
Write Cycle (1/3)
Parameter Symbol -BB55X MIN. Write cycle time /CE1 to end of write CE2 to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time /WE to output in High-Z Output active from end of write tWC tCW1 tCW2 tAW tAS tWP tWR tDW tDH tWHZ tOW 5 55 50 50 50 0 45 0 25 0 20 5 MAX. VCC 2.7 V -BB70X MIN. 70 55 55 55 0 50 0 30 0 25 5 MAX. -BB85X MIN. 85 70 70 70 0 55 0 35 0 30 MAX. ns ns ns ns ns ns ns ns ns ns ns Note Unit Condition
Note The output load is 1TTL + 5 pF.
Write Cycle (2/3)
Parameter Symbol -BC70X MIN. Write cycle time /CE1 to end of write CE2 to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time /WE to output in High-Z Output active from end of write tWC tCW1 tCW2 tAW tAS tWP tWR tDW tDH tWHZ tOW 5 70 55 55 55 0 50 0 30 0 25 5 MAX. VCC 2.2 V -BC85X MIN. 85 70 70 70 0 55 0 35 0 30 5 MAX. -BC10X MIN. 100 80 80 80 0 60 0 40 0 35 MAX. ns ns ns ns ns ns ns ns ns ns ns Note Unit Condition
Note The output load is 1TTL + 5 pF.
Data Sheet M14669EJ7V0DS
13
PD442000A-X
Write Cycle (3/3)
Parameter Symbol -DD85X MIN. Write cycle time /CE1 to end of write CE2 to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time /WE to output in High-Z Output active from end of write tWC tCW1 tCW2 tAW tAS tWP tWR tDW tDH tWHZ tOW 5 85 70 70 70 0 55 0 35 0 30 5 MAX. VCC 1.8 V -DD10X MIN. 100 80 80 80 0 60 0 40 0 35 5 MAX. -DD12X MIN. 120 100 100 100 0 85 0 60 0 40 MAX. ns ns ns ns ns ns ns ns ns ns ns Note Unit Condition
Note The output load is 1TTL + 5 pF.
14
Data Sheet M14669EJ7V0DS
PD442000A-X
Write Cycle Timing Chart 1 (/WE Controlled)
tWC Address (Input) tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tAS /WE (Input) tOW tWHZ I/O (Input / Output) Indefinite data out High-Z tDW Data in tDH High-Z Indefinite data out tWP tWR
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state.
Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE, and a high level CE2. 2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2 changes to high level at the same time or after the change of /WE to low level, the I/O pins will remain high impedance state. 3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance.
Data Sheet M14669EJ7V0DS
15
PD442000A-X
Write Cycle Timing Chart 2 (/CE1 Controlled)
tWC Address (Input) tAS /CE1 (Input) tCW2 CE2 (Input) tAW tWP /WE (Input) tWR tCW1
tDW High-Z I/O (Input) Data in
tDH High-Z
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CE1, /WE, and a high level CE2.
16
Data Sheet M14669EJ7V0DS
PD442000A-X
Write Cycle Timing Chart 3 (CE2 Controlled)
tWC Address (Input)
tCW1 /CE1 (Input)
tAS CE2 (Input) tAW tWP /WE (Input)
tCW2
tWR
tDW High-Z I/O (Input) Data in
tDH High-Z
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CE1, /WE, and a high level CE2.
Data Sheet M14669EJ7V0DS
17
PD442000A-X
Low VCC Data Retention Characteristics (TA = -25 to +85 C)
Parameter Symbol Test Condition
-BB55X, -BB70X, -BB85X -BC70X,-BC85X, -BC10X -DD85X,-DD10X, -DD12X Unit
MIN. Data retention supply voltage VCCDR1 /CE1 VCC - 0.2 V, CE2 VCC - 0.2 V VCCDR2 CE2 0.2 V Data retention supply current ICCDR1 VCC = 1.2 V, /CE1 VCC - 0.2 V, CE2 VCC - 0.2 V ICCDR2 VCC = 1.2 V, CE2 0.2 V Chip deselection to data retention mode Operation recovery time tR tRCNote tCDR 0 1.0 1.0
TYP. MAX. 3.6
MIN. 1.0
TYP. MAX. 3.6
MIN. 1.0
TYP. MAX. 2.2 V
3.6 0.05 1
1.0 0.05
3.6 1
1.0 0.05
2.2 1
A
0.05
1 0
0.05
1 0
0.05
1 ns
tRCNote
tRCNote
ns
Note tRC : Read cycle time
18
Data Sheet M14669EJ7V0DS
PD442000A-X
Data Retention Timing Chart (1) /CE1 Controlled
tCDR VCC VCC (MIN.)
Note
Data retention mode
tR
/CE1 VIH (MIN.) VCCDR (MIN.) /CE1 VCC - 0.2 V
VIL (MAX.)
GND
Note 2.7 V (-BB55X, -BB70X, -BB85X), 2.2 V (-BC70X, -BC85X, -BC10X), 1.8 V (-DD85X, -DD10X, -DD12X) Remark On the data retention mode by controlling /CE1, the input level of CE2 must be VCC - 0.2 V or 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state.
(2) CE2 Controlled
tCDR VCC VCC (MIN.)
Note
Data retention mode
tR
VIH (MIN.) VCCDR (MIN.) CE2
VIL (MAX.) CE2 0.2 V GND
Note 2.7 V (-BB55X, -BB70X, -BB85X), 2.2 V (-BC70X, -BC85X, -BC10X), 1.8 V (-DD85X, -DD10X, -DD12X) Remark On the data retention mode by controlling CE2, the other pins (/CE1, Address, I/O, /WE, /OE) can be in high impedance state.
Data Sheet M14669EJ7V0DS
19
PD442000A-X
Package Drawings
32-PIN PLASTIC TSOP(I) (8x13.4)
detail of lead end 1 32 S
T
R L 16 17 Q U
P I J S A G
H K
C
B
M
N
S
D
M
NOTES 1. Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.
2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
ITEM A B C D G H I J K L M N P Q R S T U
MILLIMETERS 8.00.1 0.45 MAX. 0.5 (T.P.) 0.220.05 1.00.05 12.40.2 11.80.1 0.80.2 0.145 +0.025 -0.015 0.5 0.08 0.08 13.40.2 0.10.05 3 +5 -3 1.2 MAX. 0.25 0.60.15 P32GU-50-9JH-2
20
Data Sheet M14669EJ7V0DS
PD442000A-X
32-PIN PLASTIC TSOP(I) (8x13.4)
detail of lead end 1 32 Q R U L
T
16
17
S
K H
N
S
D
M C
M
B
S G I P J A
NOTES
1. Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
ITEM A B C D G H I J K L M N P Q R S T U
MILLIMETERS 8.00.1 0.45 MAX. 0.5 (T.P.) 0.220.05 1.00.05 12.40.2 11.80.1 0.80.2 0.145 +0.025 -0.015 0.5 0.08 0.08 13.40.2 0.10.05 3 +5 -3 1.2 MAX. 0.25 0.60.15 P32GU-50-9KH-2
Data Sheet M14669EJ7V0DS
21
PD442000A-X
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the PD442000A-X.
Types of Surface Mount Device
PD442000AGU-9JH : 32-pin PLASTIC TSOP (I) (8x13.4) (Normal bent) PD442000AGU-9KH : 32-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent)
22
Data Sheet M14669EJ7V0DS
PD442000A-X
Revision History
Edition/ Date This edition 6th edition/ pp.6, 7 Jul. 2002 Page Previous edition pp.6, 7 Modification DC Characteristics -BB55X,-BB70X,-BB85X(MAX.) : ISB = 0.6mA 0.35mA -BC70X,-BC85X,-BC10X(MAX.) : ISB = 0.6mA 0.35mA -BC70X,-BC85X,-BC10X(MAX.) : ISB(VCC 2.7 V) = 0.6mA 0.35mA -DD85X,-DD10X,-DD12X(MAX.) : ISB = 0.6mA 0.35mA p.8 p.8 Modification AC Characteristics Ordering Information, Pin Configurations, Package Drawings, Recommended Soldering Conditions Integration of Input Waveform and Output Waveform 32-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent) Type of revision Location Description (Previous edition This edition)
7th edition/ pp.2, 4, 21-22 pp.2, 3, 19-20 Addition Oct. 2002
PD442000AGU-***-9KH
*** : Speed grades BB55X, BB70X, BB85X, BC70X, BC85X, BC10X, DD85X, DD10X, DD12X
Data Sheet M14669EJ7V0DS
23
PD442000A-X
[ MEMO ]
24
Data Sheet M14669EJ7V0DS
PD442000A-X
[ MEMO ]
Data Sheet M14669EJ7V0DS
25
PD442000A-X
[ MEMO ]
26
Data Sheet M14669EJ7V0DS
PD442000A-X
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet M14669EJ7V0DS
27
PD442000A-X
* The information in this document is current as of October, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
M8E 00. 4

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